In most integrated circuit applications, the substrate area allocated to implement the various integrated circuit functions continues to decrease. Semiconductor memory devices, for example, and their fabrication processes are continuously evolving to meet demands for increases in the amount of data that can be stored in a given area of the silicon substrate. These demands seek to increase the storage capacity of a given size of memory card or other type of package and/or decrease their size.
Electrical Erasable Programmable Read Only Memory (EEPROM), including flash EEPROM, and Electronically Programmable Read Only Memory (EPROM) are among the most popular non-volatile semiconductor memories. One popular flash EEPROM architecture utilizes a NAND array having a large number of strings of memory cells connected through one or more select transistors between individual bit lines and common source lines. FIG. 6 is a top view showing a single NAND string and FIG. 7 is an equivalent circuit thereof. The NAND string depicted in FIGS. 6 and 7 includes four transistors 600, 602, 604 and 606 in series between a first select gate 620 and a second select gate 622. Select gate 620 connects the NAND string to a bit line via bit line contact 626. Select gate 622 connects the NAND string to a common source line via source line contact 628. Each of the transistors 600, 602, 604 and 606 is an individual storage element and includes a control gate and a floating gate. For example, transistor 600 includes control gate 600CG and floating gate 600FG, transistor 602 includes control gate 602CG and floating gate 602FG, transistor 604 includes control gate 604CG and floating gate 604FG, and transistor 606 includes control gate 606CG and floating gate 606FG. Control gate 600CG is connected to word line WL3, control gate 602CG is connected to word line WL2, control gate 604CG is connected to word line WL1, and control gate 606CG is connected to word line WL0.
Note that although FIGS. 6 and 7 show four memory cells in the NAND string, the use of four transistors is only provided as an example. A NAND string can have less than four memory cells or more than four memory cells. For example, some NAND strings will include eight memory cells, 16 memory cells, 32 memory cells, or more.
The charge storage elements of current flash EEPROM arrays are most commonly electrically conductive floating gates, typically formed from a doped polysilicon material. Another type of memory cell useful in flash EEPROM systems utilizes a non-conductive dielectric material in place of a conductive floating gate to form a charge storage element capable of storing charge in a non-volatile manner Such a cell is described in an article by Chan et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device,” IEEE Electron Device Letters, Vol. EDL-8, No. 3, March 1987, pp. 93-95. A triple layer dielectric formed of silicon oxide, silicon nitride and silicon oxide (“ONO”) is sandwiched between a conductive control gate and a surface of a semi-conductive substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then changes the threshold voltage of a portion of the channel of the cell in a manner that is detectable. The cell is erased by injecting hot holes into the nitride. See also Nozaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application,” EEE Journal of Solid-State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501, which describes a similar cell in a split-gate configuration where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate select transistor.